EDA News Monday September 22, 2003 From: EDACafe _____ Cadence _____ About This Issue What Goes Around Comes Around Vertical integration is back in vogue _____ September 15 - 19, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Guess what - vertical integration is back. The disaggregated design chain has been re-aggregated, and Big is Beautiful once again. I got the news first hand from Chartered Semiconductors' Kevin Meyer, Vice President of Worldwide Marketing and Sales, in a lengthy phone call on Tuesday, September 16th. Kevin's a really articulate guy and his message was unambiguous. If you used to be an IDM and are still an IDM, you're going to be a winner going forward. Meanwhile, the fabless guys better watch out because the IDMs are reasserting control in the design, process technology, and foundry issues slated to rule the roost in the coming years. What Meyer had to say was in conjunction with several Press Releases from Chartered Semiconductor and IBM. Here is the abridged version: Chartered Semiconductor Manufacturing announced the formation of the NanoAccess Alliance in support of Chartered's NanoAccess semiconductor manufacturing technologies at 90-nanometer technologies and beyond. Under the NanoAccess Alliance, Chartered and more than 15 third-party companies are pre-qualifying 90-nanometer design solutions for earlier silicon validation and lower risk production of leading-edge IC and SoC devices. Qualification of 90-nanometer design libraries, memory components, EDA tool support, and third-party IP has been in active planning since the Chartered and IBM joint development agreement for 90-nanometer manufacturing technologies was first announced in November 2002. Silicon validation and pilot projects are currently being scheduled with first silicon multi-process wafer (MPW) runs in October 2003. Major design deliverables are set to be silicon validated by early 2004, in advance of 90nm design starts expected to gain momentum in this timeframe. As a result of the joint development, Chartered and IBM will have compatible third-party programs targeted at developing common design solutions for the resulting nanotechnology process platform. The programs are referred to as "NanoAccess Alliance" and "Ready for IBM Technology" by Chartered and IBM, respectively. The NanoAccess Alliance is an extensive ecosystem of 90 nanometer third-party library, EDA, and IP companies that currently includes ARM, Artisan Components, Inc., Cadence Design Systems, Inc., ChipIdea Microlectronics, IBM, Mentor Graphics Corp., MoSys, Inc., QualCore Logic, Synopsys, Inc., and Virage Logic Corp. Outsourced design and manufacturing-related services are also part of Chartered's NanoAccess Alliance. Design companies include Flextronics and QThink, while manufacturing service providers include Dai Nippon Printing Co., Ltd., ST Assembly Test Services Ltd., Toppan Printing Co., Ltd, and its subsidiaries, and Unitive Semiconductor Taiwan Corp. Chartered announced the immediate availability of the joint Chartered and IBM 90-nanometer design manual and SPICE models to early adopters for design prototyping. Initial process qualification for both FTEOS and low-k dielectric options is targeted for completion by the first quarter of 2004. Chartered is offering multi-project wafer (MPW) runs starting in October 2003. Chartered has qualified Dai Nippon Printing for 90-nanometer mask production. Toppan Printing and its subsidiaries are currently under qualification. Per Kevin Meyer: "During the 1990's - particularly at the beginning of the decade - virtually every semiconductor company was an IDM in the sense that they did the design, had their own process technology development, and their own manufacturing capacity. In that era, companies like Motorola and IBM did their own library development, their own DSPs, their own process development, even their own packaging in most cases." "But by 2000, few companies did any of those things - there was a very different state of affairs in the industry. There was a heavy reliance on out-sourcing relationships and a growing dependence on value-added IP. Companies became reaggregators of IP, relying on the foundries for process development and wafer development. Relationships were developed with companies like Artisan for libraries, Virage Logic for memories and memory compilers, relationships with ARM for StarIP. The designs out of these [fabless] semiconductor companies became reaggregations of IP - [even as the] emergence of the foundry model signaled the disaggregation of the semiconductor value chain. There were over 600 semiconductor companies, but only a handful owned their own foundries." "[However], everything has changed at 0.13 micron and below. Suddenly the ability to reaggregate IP has became very difficult, reversing the pendulum, and [triggering a situation where] companies that want to be successful have to design their processes to meet the application need, need to have a priori knowledge of the tools, the IP, and so forth. The whole ability to reaggreate technology from disparate companies has become extremely difficult as geometries shrink. The design challenges have become very significant. The ability to get a design right the first time at 0.13 micron is much more difficult." "[Subsequently], companies like IBM who develop processes for applications, and who have timing closure abilities, are much better situated for developing very complex designs. Going forward, the fabless guys are going to be very challenged [in trying to compete with companies like IBM]." "[Clearly], the reaggregataion challenge is very difficult right now. If you look at the number of transistors that designers are designing around, they're having to fill products up with IP from many different companies - IP that was never meant to play together. The [commercially available] tools are becoming increasing challenged. With gate oxides [reaching a point where they are] just a couple of molecules thick, having to understand how to design for manufacturing - which was one of the key differentiators in the 1990's - now presents a big, significant challenge. I believe the big companies, the old IDMs, are in the best position to prevail [in today's market]." "[Consider] from 1990 to 2002; we came down the tech road map from 1 micron plus, down to 0.13 micron. The fabless semiconductor model worked at 1 micron, at 0.25 micron, at 0.18 micron. Companies like Broadcom, Altera, Xilinx were all very successful in moving down the technology spectrum to that point. But at 0.13 micron, the industry was unable to sustain the flow. We saw signs of the challenge in the difficulties of getting 0.13 micron to market." "We also saw [in that same time period], the utilization of two new materials in the manufacturing process - the integration of copper and low-k dielectrics in the interconnect strategy. This caused [huge challenges] in the re-aggregation of IP. Additionally, mask sets went from $100,000 to $500,000 in that same period, while designs that didn't come out right with the first spin, were requiring [costly] re-spins." "[Now what we're seeing is that] although throughout the 1990's, there was a disaggregation of the value chain, at 130 nanometers and below, the value chain has to reaggregate. IBM and Chartered are working closely with Synopsys, Cadence, Mentor, ARM, Artison and others to provide the learning [to do that]. IBM is an $84 billion technology and services company, which can invest to build high-performance ASICs and microprocessors. They're taking a different approach these days - developing processes more from an application [point of view] with a priori understanding that a particular product has to go, for instance, into a high pin-count package. They're developing in-house tools for timing closure and developing those tools with an a priori understanding of the process technology needed." "And, by the way, the fact that IBM is also an enterprise systems company first means that they have no problem providing technology to their customers and partners. Through Chartered's joint development with IBM, we're trying to provide access to the learning that's gone before. IBM is an IDM and [has extensive experience developed in connection with] their own ASICs and PowerPC." "So the thing we're announcing here is really the availability to customers of the deliverables required to do a 90-nanometer design, starting off with a very comprehensive design manual that includes the design rules needed to do 90 nanometers. One of the benefits of our relationship with IBM is access to all of their innovations in material science. What Chartered brings to the relationship is a clear understanding of what the customers need to implement over a broad array of applications, how to get a design into a manufacturable state, how to integrate it into a flow that allows them to make money." "Yes, this is big news for the fabless guys as they're not going to be asked to be guinea pigs anymore to prove the process technologies. And though they'll still have a tremendous amount of opportunity to add value, they should be aware that the IDMs have folks [on staff] who can do design, develop their own tools, own their own IP, and can look at the process side and the silicon side at the same time." Should be interesting to see how all of this plays itself out over the next several years In related news releases: Mentor Graphics Corp. and Chartered Semiconductor Manufacturing announced that Mentor has joined the Chartered NanoAccess Alliance as an inaugural member. The companies says that Mentor Graphics and Chartered are collaborating to provide "extensive design support" for 90-nanometer SoC manufacturing technologies from Chartered, and that they are jointly developing 90-nanometer technology files and models for Calibre DRC, Calibre LVS, and Calibre xRC that "exploit the most advanced physical verification, parasitic extraction and resolution enhancement capabilities of the Calibre design-to-silicon platform, which is Chartered's 'golden' internal standard for design rule checking (DRC)." Chartered Semiconductor Manufacturing and Virage Logic Corp. announced they will make available Virage Logic's Technology-Optimized Platform on Chartered's NanoAccess 90-nanometer SoC manufacturing technologies. The companies say the announcement underscores the "strategic significance of their long-standing relationship" and that Virage Logic has joined Chartered's NanoAccess Alliance as an inaugural member. Virage Logic's standard cell libraries, I/O components, and memory compilers for SRAM, ROM and register files will be qualified for Chartered's 90-nanometer baseline logic process. Design libraries will be available beginning in the fourth quarter of 2003. Silicon qualification is in progress and release of fully silicon-validated libraries is expected by the second quarter of 2004. Chartered Semiconductor Manufacturing and Synopsys, Inc. announced that Synopsys has developed silicon libraries for Chartered's NanoAccess 90-nanometer SoC manufacturing technologies. In addition, the two companies say they are qualifying chip design tool flows for the NanoAccess 90-nanometer process. In addition, Synopsys has joined Chartered's NanoAccess Alliance as an inaugural member. The 90-nanometer libraries consist of standard cells, I/O components, and memory compilers, which are optimized for Synopsys' Galaxy design and Discovery verification platforms. The Synopsys offering includes multiple standard cell libraries characterized for multiple voltage thresholds, as well as new signal integrity and power management design views. Run-set and technology files are optimized for Chartered's 90-nanometer process and Synopsys' physical design tools. The two companies say they have also begun validation of a joint 90-nanometer reference design flow. Industry news - Tools and IP Accelerated Technology, the Embedded Systems Division of Mentor Graphics Corp., announced that its Nucleus RTOS was used to develop the Air Data Test Set (ADTS) 505 remote hand terminal by Druck Ltd. The ADTS 505 test set was specifically designed for use with civil aircraft and allows aircraft technicians to check the performance and readout of vital instrumentation in an aircraft cockpit. The Press Release comments: "With the skies becoming ever more crowded, a standard has been set up to allow approved aircraft to fly closer together. The RVSM (Reduced Vertical Separation Minima) standard requires that rigorous checks of the altitude-measuring instruments are not only desirable but also mandatory. These checks require a pneumatic test instrument (ADTS 505) to be attached to the pressure-sensing ports located on the outside of the aircraft. The cockpit instruments can then be checked while applying test pressures. The ADTS 505 hand terminal has transformed a time-consuming two-man operation (one technician outside with the ADTS 505 and the other in the cockpit) into a one-man operation." The test technician sits in the aircraft cockpit with the terminal and passes a cable through the cockpit window. From there he is able to read the measurement data regarding outside pressures. The technician is therefore in full control of the "flight pressures" required for any test scenario on aircraft ranging from a Cessna to a Concorde. Accelerated Technology also announced in conjunction with Xilinx, Inc. support for MicroBlaze - which Xilinx describes as "the industry's fastest FPGA-based soft processor" - with the release of the Nucleus RTOS from Mentor Graphics. The companies say that MicroBlaze core developers in the networking, telecommunication, data communication and consumer markets now have access to a complete family of RTOS products from which to build their embedded application. Also from Accelerated Technology (AT) - The company announced support for the Motorola PowerQUICC III processor family, beginning with the MPC8560 processor, with the Nucleus RTOS, Microtec C and C++ compilation tools, and the XRAY Debugger. The company says that now embedded developers have a "complete software solution available from one vendor in which to build, compile and debug their communication and networking applications." The Nucleus RTOS can scale down to as small as 23KB, for both code and data, on the PowerQUICC family of processors. Meanwhile, Insignia Solutions and Accelerated Technology (AT) announced that Insignia has licensed its Secure System Provisioning client software technology to AT to be included with its Nucleus RTOS for mobile phones. The new agreement is such that phone manufacturers using the Nucleus RTOS will be able to ship a platform with Insignia Secure System Provisioning features such as Over-The-Air Repair and Dynamic Capabilities built-in. Insignia's SSP Client, which is being licensed by AT, is a software component embedded in the terminal that enables its system software to be securely updated. Finally, and probably most importantly - Accelerated Technology announced the release of Nucleus 802.11 STA to developers requiring 802.11b or wireless Ethernet support to build their wireless application. The company says the addition of 802.11b to the Nucleus RTOS product line will allow users of the Nucleus RTOS to easily add wireless capabilities to their devices. Per the Press Release: "802.11b, or wireless fidelity (Wi-Fi), refers to a family of specifications for wireless local access network (LAN) technology. Wi-Fi, a term coined by the Wi-Fi Alliance, provides for wireless Ethernet transmission primarily between laptops and local access nodes that attach to the standard corporate LAN. While the office is a natural setting for Wi-Fi, the movement to wireless communication in the home has provided increased capabilities for personal Wi-Fi use. Cellular phones, PDAs, and handheld Internet appliances are among many devices that now carry wireless Ethernet capabilities allowing users to connect with others across the room or across the country without the limitations of physical wires." Robert Day, Director of Marketing for Mentor Graphics Embedded Systems Division, is quoted in the Press Release: "Wi-Fi, which has been a hit on the desktop is quickly becoming a must-have technology for many of our embedded customers, especially in the consumer electronics space. Because the Nucleus software dominates the commercial-off-the-shelf market for operating systems in this area, the addition of 802.11 technology to the Nucleus family of products was an easy decision to make." Aldec, Inc. announced that it has entered the embedded systems market with a hardware/software co-verification platform, CoVerT, developed for FPGA designs using soft-core microprocessors. The company says the news product combines Aldec's HDL design entry and verification software, Active-HDLT, with the new CoVer technology, which allows hardware and software teams to work in parallel on the same configuration of the design from the start of a project. Per the Press Release: "Complete debugging visibility is available to both teams at all times and throughout the entire design process. The company says that placing the processor and its related software into CoVer hardware, while putting all peripherals in Active-HDL, allows concurrent design verification by hardware and software teams. During data exchange between CoVer hardware and the Active-HDL simulator, the processor executes its program at between 100-200KHz. When not communicating with the peripherals in Active-HDL, the processor runs in emulation mode at 16 MHz, providing complete signal visibility and ultra fast debugging at any hierarchical level of the design. CoVer provides direct event or transaction-based communication between the hardware and software design sections allowing reliable and efficient debugging and verification. It eliminates the need for cables, lab time, and "stub code" and does away with having to continuously make new hardware prototypes for the software team." Aptix Corp. announced that it is shipping "the only reconfigurable hardware platform to run at multi-megahertz speeds and offer high-performance transaction-based emulation based on the Accellera SCE-MI standard-Aptix SoC Validation Lab ." The company says the new product incorporates technology from Zaiq Technologies, including Zaiq's libraries of verification IP. Charlie Miller, Senior Vice President of Marketing and Business Development at Aptix, is quoted in the Press Release: "Our Aptix SoC Validation Lab speeds up embedded electronic system validation by 1000's of times, and its use of the Accellera SCE-MI standard supports interoperability. On a 400,000 gate network-processor design, we see speed-ups of up to 4000x over a Verilog software simulator running on a Sun Ultrasparc 60. On larger designs, the improvement is greater." Barcelona Design Inc. announced that Toshiba Corp. has licensed Barcelona?s analog synthesis solutions, including its Miro PLL circuit model and process models for Toshiba's 0.13-micron and 90-nanometer processes. Richard Tobias, Vice President, ASIC and Foundry Business Unit, System LSI Group, Toshiba America Electronic Components, Inc., is quoted in the Press Release: "Barcelona's analog synthesis solution helps support our growing demand for custom SoC designs integrating several PLLs that must be custom designed each time to optimize performance. The need for an analog synthesis solution becomes even more critical for our current 90-nanometer processes to achieve higher levels of integration and lower costs. Barcelona's synthesizable PLL is a good fit for our SoCs for network, storage, and consumer applications." Cadence Design Systems Inc. and ARM announced the availability of the ARM-Cadence Reference Methodology, based on the Cadence Encounter digital IC design platform. The companies say that support for the signal integrity-enabled flow, which incorporates CeltIC crosstalk analysis and repair and VoltageStorm power grid analysis, is included in the ARM-Cadence Reference Methodology. The Reference Methodology is described as a "shrink-wrapped reference flow that provides predictable RTL-to-GDSII implementation for ARM Partners and enables predictable performance, power and area results." The methodology also is intended to provide accurate abstract models for SoC integration. Of particular interest - the new ARM-Cadence Reference Methodology includes the newly acquired Verplex Conformal logic equivalence checker. The companies say that the Reference Methodology will be available from ARM in Q4 2003 (beta available now) and will support the ARM946E-S core initially, and that support for all other ARM soft cores will be provided in the future. Also from Cadence - The company announced immediate availability of the Intel IXP2800 design-in kit for Cadence high-speed design solutions that include SPECCTRAQuest Signal Integrity (SI) Expert and Allegro PCB Design Expert. Cadence says the IXP2800 design-in kit using Intel data/IP can shorten systems companies' time to design in the Intel IXP2800 network processor on PCB systems by eight to 12 weeks. The Press Release says, "Design-in kits make PCB designers instantly more productive. This new Cadence design-in kit enables engineers to develop optimal constraints for their product and to subsequently use these constraints to drive PCB floorplanning, routing and verification processes." Similarly from Accelerated Technology - The company announced a version of the Nucleus RTOS for the Intel IXP4XX product line of network processors, including initial support for the Intel IXP425 network processor. The company says this Nucleus release will give developers using the IXP425 a "full-featured real-time kernel to address the needs of building many wired and wireless applications for the home, small office/home office (SOHO) and small- to medium-enterprise (SME) market segments." The Intel IXP425 network processor is described as a" highly integrated, versatile single-chip processor that can be used in a variety of products that need network connectivity and high performance to run their unique software applications." Finally from Cadence - A major announcement regarding Virtuoso. Per the Press Release": "Cadence Design Systems, Inc. announced the Cadence Virtuoso custom design platform, the world's first comprehensive platform for fast, silicon-accurate custom, analog, RF and mixed-signal design. The Virtuoso platform boasts the industry's only specification-driven environment, the first multi-mode simulation utilizing common models and equations, up to greater than 10x faster accelerated layout, advanced silicon analysis for 130 nanometers and below, and a full-chip, mixed-signal integration environment." "The Virtuoso platform is available on both the industry-standard OpenAccess database and the popular Cadence CDBA database. With the Virtuoso platform, design teams can quickly design silicon that is right and on time at process geometries from 1 micron down to 90 nanometers and beyond." "With this platform, Cadence is upgrading all of its existing custom technologies and shipping several new products. The new Virtuoso Multi-mode Simulation provides SPICE, FastSPICE, AMS, and RF capabilities - all utilizing common syntax, models, and equations. Virtuoso LE Turbo adds design-rule driven, QuickCell parameterized cell specification, and wire-to-wire editing capabilities to Virtuoso LE. The platform also adds Virtuoso AMS Silicon Analysis for 130 nanometers and smaller circuits, and Virtuoso HF-AMS silicon analysis, which includes additional capabilities for greater than 1GHz circuits." Jean Pierre Geronimi, CAD Director of Central R&D Design Automation at STMicroelectronics, is quoted in the Press Release: "The Cadence Virtuoso custom design platform will be the backbone of our next-generation mixed-signal flow. Our decision was mainly driven by the productivity gain we have seen both in the point tools and the new OpenAccess database infrastructure. More specifically: for tools, we have much appreciated the enhancements to Virtuoso, CCAR power routing and Preview, particularly in the area of 130- and 90-nanometer support, where we contributed with our process specifications, while, in the OpenAccess space, we were very pleased with the capacity and performance seen in the new OA-native Virtuoso Chip Editor for managing the final Chip Finishing phase of the Physical Design." Synchronicity announced that, effective immediately, its Developer Suite supports the new Cadence Virtuoso custom design platform. Synchronicity says it has been testing its Developer Suite with the new Cadence software since the beginning of the year, and that it is now "fully proven with the new and existing Cadence applications that run on either the new generation, industry-standard OpenAccess database or the popular Cadence CDBA database." Magma Design Automation Inc. announced RTL-to-GDSII support for the AMD Opteron processor and AMD64 architecture. An AMD64 version of Magma's complete IC implementation system is currently in limited release with its key ASIC and COT partners, with a general release planned for early December 2003. Magma says it is the first EDA vendor to port its entire line of RTL-to-GDSII software to the AMD Opteron processor. Palmchip Corp. and Oki Electric Industry Co., announced that Oki has licensed Palmchip's BK-3710 IDE Ultra ATA 133Mhz storage connectivity IP product. Toshiyuki Tahara, Vice President and General Manager, LSI Design Division of Silicon Solutions Company at Oki Electric, is quoted in the Press Release: "We are looking forward to working with Palmchip in the coming months. Their responsiveness and support during the evaluation process was excellent. We will be integrating the BK-3710 controller in several future products." PMC-Sierra, Inc. announced that the RM7000C has received the highest out-of-the-box scores ever recorded for a MIPS-based embedded microprocessor. EEMBC Certification Labs (ECL) tested the RM7000C 64-Bit MIPS-based processor at 625MHz using benchmark suites that measure the expected device performance in networking and office automation systems. The five-stage pipeline RM7000C achieved and demonstrated the highest performance and lowest power for any superscalar processor with in-order execution. Markus Levy, EEMBC President, is quoted in the Press Release: "The EEMBC benchmark's ability to accurately model real-world behavior allows users to directly infer the performance of the RM7000 in networking and office automation applications. These first certified EEMBC scores from PMC-Sierra help to demonstrate the benefits of the RM7000's advanced microarchitecture." Sagantec has released Sagantec Tool Set version 7 (STS7). The company says the new version updates all Sagantec custom IC design products: SiClone, SiFix, Companion, and Anaconda, and that "STS7 delivers bigger design capacity, higher speeds, support for 90-nanometer and 65-nanometer process design rules, and flow integration with the newly introduced Cadence Virtuoso custom design platform running on both the industry-standard OpenAccess and the popular Cadence CDBA databases." Sagantec says it is a member of the OpenAccess Coalition, has worked closely with Cadence to ensure industry-wide open interoperability of the STS7 products with the new Cadence Virtuoso custom design platform version 5.033 running on OpenAccess database. The company also says it will continue to work with Cadence, the Silicon Integration Initiative (Si2), and the OpenAccess Coalition members, to provide ongoing support for the OpenAccess standard and OAC members' implementations. Rambus Inc. and Synopsys, Inc. announced a collaboration to develop a hardware platform that demonstrates the interoperability of their PCI Express IP "solutions." The companies say that Rambus is providing the RaSer PHY for PCI Express applications, and Synopsys is providing the DesignWare PCI Express Endpoint Controller Core. Synopsys and Rambus say they expect to demonstrate a working PCI Express solution that provides "seamless operation and lower-risk implementation for chip developers at the PCI Express Interoperability Workshop in the fourth quarter of 2003. Per the Press Release: "The platform demonstration will consist of two boards - a motherboard, constructed by Synopsys, using FPGAs to house the Synopsys Endpoint Controller with driver software, and a daughterboard consisting of Rambus' PHY IP. The interface between the two boards will adhere to the industry-standard PIPE (PHY Interface for PCI Express) specifications. Synopsys' motherboard will include three protocol layers (the Logical PHY layer, the Data Link layer and the Transaction layer), while Rambus' daughterboard will include the analog PMA (Physical Media Attachment) sub-layer and the PCS (Physical Coding Sub-Layer)." Likewise, Synopsys, Inc. and Artisan Components, Inc. announced a collaboration to develop a hardware platform that validates the interoperability of their PCI Express IP solutions. The companies say the platform conforms to the PIPE (PHY Interface for PCI Express) standard, and that they plan to develop a mother/daughterboard platform utilizing Synopsys' DesignWare PCI Express Endpoint Controller Core and Artisan's PCI Express PHY IP. Synopsys and Artisan plan to present the offering in the fourth quarter of 2003. Per the Press Release: "The platform demonstration will consist of two boards: a Synopsys-developed motherboard including FPGAs to house the Synopsys Endpoint Controller with driver software, and a daughterboard consisting of Artisan's PHY silicon. The interface between the two boards will adhere to PIPE specifications. Synopsys' motherboard will include three critical protocol layers - the logical PHY layer, the data link layer and the transaction layer. Artisan's daughterboard will include a complete serial link including mux/demux, 8b/10b encode/decode, elastic buffer and clock recovery circuitry that will be compliant with the PCI Express Base 1.0a Specification. Testability features for the Artisan daughterboard include built-in self-test (BIST), serial and parallel loopbacks, IDDQ (power down) and pseudo random bit sequence (PRBS)." Also from Synopsys - The company announced that Toshiba Corp. has taped out a high-performance digital image processor chip using Synopsys DFT Compiler SoCBIST's deterministic logic BIST capability. The device has 6 million gates and was designed using Toshiba's TC280 0.13-micron process. Toshiba reported a 10x reduction in tester time and a greater than 100x reduction in test data volume using the tool. Antun Domic, Senior Vice President and General Manager for the Synopsys Implementation Group, said: "Toshiba provided key guidance to Synopsys on their requirements in test quality, cost, and diagnostics, and has built a very impressive production methodology and design flow that fully and effectively utilizes SoCBIST's capabilities. We look forward to our continued collaboration with Toshiba and to advancing robust and production-ready manufacturing test methods for their next-generation products." Verisity Ltd. announced eAnalyzer, an "intuitive static analysis and verification methodology compliance system that simplifies verification environment development." The company says the methodology is designed to allows engineers to adopt best practices at the module and system level by supporting Verisity's eReuse methodology (eRM) which is described as the foundation of the recently announced System Verification Methodology (sVM). The company says eAnalyzer facilitates verification component reuse, enabling easy creation of highly automated, high-quality, consistent chip-level verification environments using best-known guidelines. eAnalyzer will also support the IEEE P1647 version of the e verification language. Also from Verisity - The company announced a new methodology, and "tightly coupled technology, that enables a 10x increase in productivity and improved predictability for automating the verification process at the SoC and system level. The System Verification Methodology (sVM) encapsulates comprehensive guidelines that effectively transfer specialized verification expertise, while new technology in the Specman Elite verification process automation solution and library additions simplify adoption and enable productivity gains required for the largest nanometer era designs." The company says that sVM provides productivity gains greater than 10x in the composition of SoC and system-level verification environments by raising the level of abstraction to the sequence level (combinations of transactions), while multi-channel constraint solving and generation makes it possible to get the same coverage goals in one-tenth the number of verification cycles as compared to directed testing or other customized methods. The company says their announcements this week represent "another major step forward for Verisity's Verification Process Automation (VPA) strategy, going well beyond language and testbench toward automating and simplifying the increasingly complex process from executable test plans to verification closure. Verisity's VPA solutions combine pre-packaged, proven best practices with automation, analyses, and libraries in a form that can be readily adopted by the mainstream engineering community." ViASIC Inc. and Manhattan Routing Inc. (MRI) annouced a "strategic" partnership to enhance the timing closure flow and optimize low power design in large ASIC designs. Customers using MRI's optimization tool suite and ViASIC's routing technology will benefit by being better able to optimize the last few problem nets in a design. The companies say that the partnership will ensure that all design data exchange issues are resolved before customers use both companies' tools, and will give mutual customers "seamless" communication between the tools. ViASIC' s routing tool can use data from MRI's Physical Window and Optimization Cockpit tools either pre- or post-routing to optimize a customer's standard-cell design. Coming soon to a theater near you Ansoft Global Seminars 2003 - The company says these events will demonstrate how experts are threading electromagnetic analysis up front in their processes and rapidly creating optimized, high-performance designs. High-speed designers will hear about massively parallel supercomputer design, high-speed differential signaling, high-speed PCB signal launch, and so on. High-frequency designers will hear about optimizing high-performance LTCCs, amplifiers with Doherty configurations, cavity filter and diplexer deisgn, and so on. The seminars are happening in variuos venues throughout Asia, Europe, and North America. ( www.ansoft.com/DeliveringPerformance ) Newsmakers OEA International, Inc. announced that it has appointed two new distributors in India - ICON Design Automation Pvt. Ltd. - and Israel - AMOS Technologies, Ltd. - and added a dedicated sales representative in Europe. The company says the representatives will cover sales and coordinate product support. OEA recently opened a new sales office in the U.K. SpiraTech Ltd. has announced that they have raised venture capital from two separate investment funds and appointed three individuals to the company's board. The company says the funding will be used to expand the company's existing customer base and develop its commercial potential on a global basis. The three new appointees include: David Stewart, CEO of CriticalBlue, who has joined the SpiraTech board in the capacity of non-executive Chairman, Chris Rose, Co-founder of Saros, who joins as a non-executive director, and Simon Calder, who has been named Vice President of Sales and Marketing for SpiraTech. Steve Hodgson, Co-founder and Managing Director for the company, is quoted in the Press Release: "Our industry now seems to be coming to the unanimous opinion that the migration from RTL to ESL has finally begun. In the past six months we have seen a dramatic increase in interest for our particular solution from SoC developers and other EDA companies alike. It is our aim to use this new capital to grow our team and to address the market needs for our products." Teseda Corp. announced the appointment of William Lattin to the company's Board of Directors and Roger Bitter to the role of Vice President of Sales. Lattin's resume includes: work at Motorola, Vice President and General Manager of Intel's System Group for 11 years, President and CEO of Logic Automation through its merger with LMSI to form Logic Modeling, President and CEO of Logic Modeling until the Synopsys acquisition, member of Synopsys' Board of Directors and Executive Vice President of Synopsys. Lattin has a PhD, holds seven patents, is a founding member of VHDL International, and a senior member of IEEE. He also serves on the Boards of six additional companies. Roger Bitter has 20+ years of sales experience in the EDA, IP, and ATE industries. Most recently he was Worldwide Vice President of Sales and Marketing at Xpedion. Previously, he worked at Virage Logic, Magma Design, Sycon Design, and was President and CEO of TSSI Inc. through to its acquisition by Credence. Bitter has a BSEE, an MS in Management Science, and an MBA in Finance from West Coast University. Verisity, Ltd. announced that Pierre Lamond has retired from the company's Board and that Douglas Fairbairn has joined its board. Lamond, who has been on Verisity's Board since August 1997, will now focus on his private venture portfolio companies. Meanwhile, Fairbairn has over 30+ years of executive management experience in the semiconductor and EDA industries. Per the Press Release, he is a "recognized founder of the ASIC industry and system-level design segment of EDA. His previous positions include: Founder of VLSI Technology and General Manager of its ASIC Division, Founder and CEO of Redwood Design Automation, General Manager of the Alta Division at Cadence, President of the VSI Alliance SoC industry consortium, and President and CEO of Simutech Corp. Doug was also founder and Publisher of VLSI Design Magazine. Early in his career, he was a systems engineer at Xerox Palo Alto Research Center. He has BSEE and MSEE degrees from Stanford University." In the category of... Legal wrangling It's always better not to discuss the legal carryings on in this industry, but the following recent news release seemed pretty interesting nonetheless: Nassda Corp. commented on the rulings and orders recently issued in California state court by the discovery referee with respect to its litigation with Synopsys, Inc. Per Nassda's Press Release: "As Nassda reported in January 2003, the discovery referee then issued an order that created certain 'rebuttable presumptions' in favor of Synopsys. In September 2003, the discovery referee also ruled that attorney client privilege does not apply to some of the communications between Nassda and its former counsel regarding the computer media addressed in the first ruling." Sang Wang, CEO of Nassda, is quoted in the Press Release: "Nassda believes that it has not withheld any evidence and does not expect these communications to show any wrongdoing or withholding of evidence by Nassda or its former counsel. Synopsys has been ordered by the court to answer questions that address the lack of facts supporting Synopsys' claims. Other motions to compel Synopsys to answer such questions are before the referee. There have been many preliminary rulings in this case, and we expect many more as the current discovery process goes forward. Some of the rulings are favorable to us and others are not. None of these rulings, however, resolves any of the claims made by Synopsys in the case and the trial judge or jury will reach their own conclusions based upon the evidence presented at trial. Nassda intends to present evidence at trial to show that it did not take or use Synopsys trade secrets. Nassda's HSIM product is, in fact, superior to Synopsys' products and was developed independently by Nassda's engineers. Over 200 companies and organizations worldwide have adopted Nassda's new-generation nanometer solutions. The difference our customers see in the performance and capabilities of our products is due to our own innovative development. We will continue to focus on innovation and customer support and will not be distracted by anti-competitive legal maneuvers." --Peggy Aycinena is a Contributing Editor and can be reached by clicking here . You are subscribed as: [dolinsky@gsu.by]. CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. To change your subscription details, including format and frequency, or to unsubscribe, please click here or visit http://www10.edacafe.com/nl/newsletter_subscribe.php. If you have questions about EDACafe services, please send email to edaadmin@ibsystems.com . Copyright c 2003, Internet Business Systems, Inc. All rights reserved.